Integrated semiconductor memories have word lines and memory cells with selection transistors whose gate electrodes are connected by the word lines. There are semiconductor memories in which each word line has a longer main word line and many shorter line segments, each interconnect segment being connected to the respective main word line via at least one contact hole filling.
After fabrication, integrated semiconductor memories are subjected to an electrical functional test, during which the entirely satisfactory functioning of the semiconductor memory is checked. In particular the high density of miniaturized component structures requires such tests since chip failures may arise even on account of small positional deviations of microelectronic structures. Temporal alterations in the structures themselves can also have the effect that over the course of time, by way of example, originally conductive structures acquire high resistance and a current flow is thereby made more difficult or interrupted. Such alterations may be caused by electromigration or other effects.
In order to prevent ageing-dictated defects of semiconductor memories, semiconductor memories are subjected to a burn-in test after they have been produced, during which test they are stressed, i.e., loaded thermally and/or electrically to a greater extent than in the later customary operational mode. Ageing-dictated alterations are thereby accelerated and defective semiconductor chips are sorted out prior to delivery to customers. Those semiconductor memories which pass the burn-in test are less susceptible to ageing-dictated failure.
A burn-in test achieves higher loading of a semiconductor memory by virtue of the semiconductor memory being operated at an excessively increased temperature and with an excessively increased internal operating voltage. During the artificial pre-aging, a saturation behavior occurs in the frequency of defects that occur, so that after saturation has been reached, the failure probability of the semiconductor memories that have not yet failed is relatively low.
Devices for carrying out a burn-in test have a multiplicity of terminals to which a multiplicity of semiconductor memories are connected simultaneously. The clock frequency of the burn-in systems operating in parallel is limited on account of the multiplicity of terminals and the simultaneously tested semiconductor memories and is of the order of magnitude of approximately 5 to 10 MHz. Such component structures of a semiconductor memory which, in normal operation of the memory, are operated with significantly higher switching times of 100 MHz or higher cannot be switched in accelerated fashion by means of burn-in systems. For contact hole fillings, in particular, hitherto there has been no possibility for artificially pre-aging them. However, on account of their small lateral dimensions, contact hole fillings produce no or only a poor conductive electrical connection even in the event of small positional errors. Contact holes are used for word lines, for example, by means of which memory cells are accessed during operation of the memory, for instance when storing, reading out or when refreshing information. Word lines often comprise metallic interconnects, referred to here as main word lines, and a multiplicity of interconnect segments, which are in each case electrically conductively connected to the main word line by a contact hole. Each interconnect segment forms the gate electrodes of a plurality of selection transistors.
In the case of a segmented word line, the selection transistors are in each case connected to the main word line by the interconnect segments. The main word line generally comprises a metal. The interconnect segments usually comprise polysilicon. On account of the polycrystalline structure of polysilicon, particularly in the case of high switching times, the signal propagation is not effected rapidly enough and is attenuated as the length of the polysilicon line increases. Therefore, only relatively short interconnect lengths in each case are produced by segments made of polysilicon, the metallic main word line, which exhibits better conductivity, being provided in a higher metal plane, polysilicon interconnects in each case being connected to the main word line via a contact hole filling. The metallic main word line extends over larger distances than the individual interconnect segments.
On account of the close distance between the word lines, which in each case corresponds only to the minimum feature size of the technology used, the contact hole fillings cannot be produced wider than in accordance with the minimum feature size. A burn-in test stressing the contact hole fillings between the main word line and the interconnect segments of a word line would have to reverse the charge of the capacitance of a low-resistance interconnect segment for the purpose of switching and for the purpose of obtaining a current flow through the contact hole filling. The time duration required for this means that it is not possible to carry out a burn-in test in which the ageing process of contact holes is accelerated relative to normal operation of the memory.